Deepak Chandrasekar

About Deepak Chandrasekar

Hello! Opportunity for improvements is what I am passionate about. A Passionate Electrical Engineer with a Master\'s Degree and four years of experience in DFTINTERESTS: ASIC/SOC Design For Testability (DFT) • DFT implementation for SCAN Insertion/Compression and ATPG pattern generation for SAF/TDF/CA • Experience in analyzing and improving the test coverage, DFT/ATPG DRC\'s, simulating and debugging scan patterns in unit delay and timing aware GLS env • Experience in post silicon debug of scan patterns and pattern bring up on tester, diagnosing the scan failures on tester, shmoo improvement(crack/ceiling) and yield enhancement • Experience in Verilog RTL, Synthesis, Static Timing Analysis, CDC. • Good Knowledge in Boundary Scan/JTAG 1149.1, MBIST implementation, at-speed testing, IDDQ testing and fault models like SAF, TDF, PDF, Bridging, SDD, Cell aware faults. • Good Knowledge of ASIC Design Methodology(Flow) from RTL to GDS2 • Knowledge of Clock Domain Crossing (CDC) & Computer Architecture-TECHNICAL SKILLS: • Programming/Scripting Languages: C, Perl • Hardware Description Languages (HDL)- Verilog, VHDL • ATPG tools: Synopsys Tetramax, TestKompress • SCAN Insertion: DFT Compiler • MBIST- Mentor LV MBist (beginner) • HDL Simulators: Synopsys VCS, Mentor ModelSim • Synthesis: Synopsys DC • STA(Static Timing Analysis): Synopsys Primetime • Operating Systems: Windows, Linux/Unix, Mac-Reach me at r••••••••@gmail.com

Experience

1. Staff Cpu Dft Engineer

   美商高通國際股份有限公司

   Jan 2025 — Present · Austin, TX, US

Education

• Wright State University

  Master’s Degree, Digital Design and Design For Testability (DFT)

  2016 — 2018

• Panimalar Institute Of Technology

  Bachelor’s Degree, Electrical and Electronics Engineering

  2010 — 2014