Deepak Anand Ravindran

About Deepak Anand Ravindran

I am a post-Silicon Test and Validation Engineer at Intel for the last 8 years. Prior to that I have worked as a Memory Circuit Design Engineer at Dolphin Technology Inc, San Jose, CA and an IC Product Engineer at Broadcom, Irvine, CA and Embedded Systems Hardware Engineer at CDOT Alcatel-Lucent Research Center, India for two years and was an effective and enterprising team player. Between industry experience and graduate school education, I bring to the table solid hardware knowledge, both at chip-level and system-level.

Experience

1. Senior Product Development Engineer

   Intel

   Jun 2016 — Present

   Test/Manufacturing Engineer June 2018 to PresentDrove test plan generation, pre-Si simulation/debug of ATE vector/stil file and final test generation for ATE (Advantest and custom Intel ATE) to enable Sort/FT Power On and production HVM screens for Intel FPGAs. Tests covered patterns for die Reset/Config (firmware load and FPGA configuration sof load), Memory BIST for SRAM/RF arrays, ATPG, JTAG/IJTAG and parametric/leakage Icc/power measurement. Delivered functionally accurate test patterns generated from MentorGraphics Tessent IJTAG suite while validating through device simulator (Synopsys VCS/DVE/Verdi suite) pre-silicon. Have hands-on tcl and python scripting work. Have good knowledge of industry standard MBIST algorithm sequences and memory structural fault coverage, as well as ATPG content such as Chain,SA,TDF and FA (EDT Bypass, DPort) patterns. Developed tests to meet performance, test time and yield optimization, and rapidly brought them up on silicon successfully during Wafer Sort/FT Power-On. Worked on test coverage and yield improvement, PVT characterization, stress/reliability failure debug, assisted in FAFI and performed parametric JMP data analysis to enhance test coverage for successful PRQ.Post-Silicon Validation Engineer June 2016 to June 2018Drove post-silicon IP validation/PVT characterization of temperature sensor/thermal diode and voltage sensor IPs on Intel FPGAs. Bench tests using tcl automation scripts and VISA APIs. Engaged with Design and Field Application engineers to ensure quality and published IP specs on the Stratix10 datasheet. Performed similar duties on validation of device JTAG IO timing characterization and Boundary Scan. Debugged/root-caused customer issues. Drew up test plan for the firmware loading/configuration, HSSI IO ACJTAG Boundary Scan and PVT Sensor calibration tests for development/integration into test program.

Education

• DAV Boys Senior Secondary School, Gopalapuram,Chennai

  Mathematics,Physics, Chemistry, Computer Science

  1992 — 2006

• University of Southern California

  Master of Science (M.S.), Electrical Engineering

  2013 — 2015

• National Institute of Technology, Tiruchirappalli

  Bachelor of Technology (B.Tech.), Electronics and Communication Engineering

  2007 — 2011

Skills

• Cadence Virtuoso Schematic Editor
• Computer Architecture
• Cadence Allegro Physical Viewer for Pcb Design Flow
• Systemc
• Fpga
• Verilog Hdl
• Asic
• Vhdl
• Cadence Virtuoso Layout Suite
• Testing
• High-Speed Digital Design
• Xilinx Ise
• Soc
• Trace32
• Synopsys Tetramax Atpg
• Cadence Encounter Soc Auto P&R
• Ncsim
• Board Bring-Up
• Perl
• Embedded Systems
• Cadence Simvision,
• Syntricity Dataconductor
• Matlab
• Conformal Lec
• Synopsys Primetime Sta
• Debugging
• Simplescalar Simoutorder Cpu Performance Simulator
• Algorithms
• Altera Quartus Ii
• C++
• Field-Programmable Gate Arrays (Fpga)
• C
• Vlsi
• Verilog
• Cadence Orcad Capture for Pcb Schematic Flow
• Xilinx Chipscope
• Modelsim
• Synopsys Design Compiler
• Mentor Graphics Dxdesigner for Pcb Schematic