Deepak Agrawal

About Deepak Agrawal

I am a graduate in Electronics & Communication Engineering from ABES Engg College, Ghaziabad. I am an enthusiast of Digital Design and Verification. Within the experience that I possess so far, I have gained knowledge of Verilog, System Verilog, RTL-Creation, RTL-debugging, RTL-Synthesis.• Knowledge of RTL creation (from scratch) involving communication protocols with configuration interfaces, pipelined and non-pipelined architectures for calibration systems (keeping CDC and LINT in check).• Have experience of working with cross-functional teams involving Synthesis, PnR and other integration teams.• Knowledge of preparing Verification environments using SV (from scratch) and maintaining Verification plans.• Worked on Behavioral Simulations, Post-Synthesis Simulations & Gate-Level Simulations.• Prepared Automated Regression Verification flows (from scratch) using TCL.• Worked on A & MS Verification.• Have worked on protocols like SPI, UART, APB. • Knowledge of Unix, Bash, TCL, Python.• Tools - Xcelium, Questa-Sim, Vivado, Virtuoso, Genus.

Experience

1. Senior Asic Digital Design Engineer

   Synopsys Inc

   Oct 2024 — Present · Noida, IN

Education

• ABES Engineering College

  B.Tech, Electronics and Communication Engineering

  2016 — 2020