Deepak Verma
Intel | MS(Research) IEC IIT Delhi | In-Memory Computing | Memory circuit design | SRAM | NVM | Ex- Quest Global
- Role
- Soc Design Engineer at Intel
- Location
- New Delhi, DL, IN
- LinkedIn followers
- 500 followers
About Deepak Verma
Currently working as Physical Design Power Delivery Engineer at Intel Bangalore.Enabling better computing with less power-MS(Research) in Integrated Electronics and Circuits, NVM group, EE Department, IIT Delhi.Researcher and VLSI enthusiast with experience in RTL2GDSII flow, circuit and layout design using open-source & industry tools, knowledge of Digital Electronics and VLSI concepts(STA, CTS, ECO, Signal Integrity, Power), willing to learn more and become proficient.Area of interest: SRAM/RRAM Memory Design for in-memory computing(IMC) architectures, Compute In-Memory(CIM), energy-efficient IMC architecture, Analog IMC-based Hardware Acclerator design, OTP/PUF architecture, Digital design, Physical Design flow, Comparators for IMC circuits, Open-source IMC design.
Experience
Soc Design Engineer
Jul 2024 — Present · Bengaluru, IN
Working as a Physical Design Power Delivery Engineer.2. Analyzing the power dissipation of the design and providing feedback for low-power consumption.
Education
Indian Institute of Technology, Delhi
MS(R)
2021
Indian Institute of InformationTechnology,Sonepat
Bachelor of Technology
2014 — 2018
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