Deepak S
Principal Design Engineer
- Role
- Principal Design Engineer at Cadence
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Deepak S
IP design engineer with a demonstrated history of working in the semiconductor industry, specialized in RTL design for ASIC.Working in TL layer of latest gen PCIe controller. Experience includes architecting and developing microarchitecture for ARM based systems from scratch and bring-up, peripheral IPs, telecom IPs, serial flashes, optical networking IPs.
Experience
Principal Design Engineer
May 2024 — Present · Bengaluru, IN
IP Design - PCIe controllerworking on latest gen TL layer: design and microarchitecture of credit handling & TLP handling blocks, also designed and architected various AXI blocks inside the PCIe controller
Education
National Institute of Technology, Tiruchirappalli
Bachelor of Technology (BTech), ECE
2011 — 2015
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.