Deepak Kumar
Physical Design Engineer
- Role
- Design Engineer at Apple
- Location
- San Diego, CA, US
- LinkedIn followers
- 500 followers
About Deepak Kumar
GPU Top-level & multiple blocks PNR, Timing, DRC, PDN, LVSGPU Flat FV/CLP SignoffBlock-level PNR, Timing analysis, DRC & LVS Low power block PNR implementation Chip Level FloorplanChip Power Planing for multiple ON-OFF domainsIORing DesignBump Placement & RDL RoutingPlace & Route: Synopsys ICC, Cadence EDI(SOC Encounter)Extraction Tools: StarRC STA: Synopsys PrimetimePhysical Verification: Calibre, ICV IR Drop Analysis: Redhawk LEC: Cadence ConformalSynthesis: Design Compiler, Cadence RCCustom Design: VirtuosoLanguages: Shell scripting, TclTechnology Node: 4nm, 5lpe, 7ff, 10lpe, 22nm, 14nm,45nm, 28FDSOI,180nm
Experience
Design Engineer
Jan 2023 — Present · San Diego, CA, US
Education
UTU
Bachelor of Technology - BTech, Electronics and Communications Engineering
2007 — 2011
IIVDT
Advance Diploma in VLSI, VLSI, RTL Design, Synthesis, PNR & STA
2010 — 2011
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