Deepak Kadappanavar
Lead RFIC Layout Design Engineer at Qualcomm
- Role
- Lead Rf Layout Design Engineer at Qualcomm
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Deepak Kadappanavar
VLSI professional with 10+ years of experience as Layout Design Engineer. • 1+ years of experience as Analog/IO Layout Design Engineer at Sankalpsemi.• 2.5 years of experience as Analog Layout engineer at KarMic for theclient Texas Instruments.• 4 months experience as Standard cell layout engineer at KarMic for theclient Texas Instruments.• Worked on AMPLIFIER, LDO and LEVEL SHIFTER with 45nm and180nm CMOS technology.• Knowledge of CMOS VLSI fabrication process flow.• Excellent technical skills and deep understanding of layout design issues and how to mitigate them such as the following- Electro-migration- Latch-up- Antenna Effect- Electro-Static Discharge(ESD)- Parasitics- Well Proximity Effect/LOD Effect- DFM issues and othersTech Nodes-Intel 14 ffTSMC 28nm,45nm,180nmSMIC 28nmExpertise:Layout/Design Tools:• Cadence Virtuoso XL• Cadence Virtuoso Layout Editor• Cadence Virtuoso Schematic Composer• Cadence Orcad Pspice Capture.• Ltspice,ngSpiceVerification Tools:• PVS, ASSURA, LVS, DRC(Cadence)*(Verification - DRC, LVS, RC Extraction, Antenna,EM/IR)Others:• Unix, Linux.• MS office (Excel, Powerpoint, Word)
Experience
Lead Rf Layout Design Engineer
Dec 2023 — Present · Bengaluru, IN
Education
Visvesvaraya Technological University
Bachelor of Engineering
2007 — 2011
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