Deepak Jena
Post-Silicon Validation & Electrical Characterization of SERDES IPs || Staff Engineer - Qualcomm || Ex-Broadcom
- Role
- Staff Engineer at 高通
- Location
- San Diego, CA, US
- LinkedIn followers
- 500 followers
About Deepak Jena
Engineering Lead | Strong background in Post Silicon Validation and Electrical Characterization of USB4, PCIe & other Gigabit SERDES designs | Signal/Power Integrity Analysis of UltraHighSpeed IPs | Active WG member of PCIESIG/USBIF | Alma: MTech in Wireless Communications | Developing End-to-End Characterization platform for SnapDragon Chipsets | Skilled in AI agentic flow development,Data Analysis with Advanced Python | C# and Ruby |
Experience
Staff Engineer
Feb 2017 — Present · US
Leading team of engineers for both Premium and Value-Tier SnapDragon Compute/Modems/Severs/Automotives chipsets focused on HSLink interfaces post silicon validation-SI/PI analysis of various HS interfaces/Platform PCBs for multiGigabit applications-Post Silicon Electrical characterization of HSLinks (like PCIE, USB, MIPI, GMII etc) on various SnapDragon SoC platforms-Evaluation & Characterization of SoC level mixed signal SERDES PHYs-Performing critical Debug activities on RMA units for accelerated RCA analysis-Close collaboration with IP, System, PE & ATE team to ensure effective FA, isolation of design errata as well as timely validation of critical silicon revision fixes- Conceptualization and Implementation of Python/.Net based complex algorithms to speed-up test efficiency by multi-fold. Especially targeted at RF applications-Developing Python/.Net based high end instrument drivers for system level integration of SoCs.
Education
Birla Institute of Technology, Mesra
Master of Technology (MTech), in Wireless Communication
2012 — 2014
Skills
- Embedded Systems
- Labview
- C
- Allegro
- Post Silicon Validation
- R&D
- Dft
- Simulations
- Testing
- Debugging
- High Speed Digital Design
- Pcb Design
- Rf Circuits
- Semiconductors
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