Deepak Garg

About Deepak Garg

16+ years of experience in ASIC Design & Verification for wireless IPs.Experience in system level analysis, H/W - S/W partitioning, Design, Verification and Validation support of H/W accelerator sub-modules implementing the advanced receiver algorithms for LTE wireless Modem.Specialties:ASIC design & verification for wireless domain.Verilog, VHDL, System Verilog, PERL, C++Good understanding of ASIPs & their design.Good understanding of 3GPP LTE physical layer specification and receiver channel estimation & detection algorithms for wireless communication systems.Hardware-Software partitioning & system level analysis of Layer 1 for LTE baseband modem.Expertise in development of Testbench architecture, Verification plan & Testbench using UVM

Experience

1. Engineer, Sr Staff Mgr

   Qualcomm

   Dec 2020 — Present · IN

Education

• Maheshwari Public School, Jaipur

  Senior Secondary, English, Physics, Chemistry, Maths, Computer Science

  1996 — 2002

• Indian Institute of Technology, Madras

  B.Tech & M.Tech, Electrical Engg - Communication Engineering

  2003 — 2008

Skills

• Amba Ahb
• Application-Specific Integrated Circuits (Asic)
• Vlsi
• Vasip
• Perl
• Verilog
• Modelsim
• Rtl Coding
• Lte
• Soc
• Digital Signal Processors
• Functional Verification
• Ip
• C++
• Xilinx
• Systemverilog
• Debugging
• Vhdl
• Wireless Technologies
• Very-Large-Scale Integration (Vlsi)
• Rtl Design
• Processors
• Asip
• Arm
• Tcl
• Wireless
• Wireless Communications Systems
• 3g
• Hardware Architecture
• Algorithms
• System on a Chip (Soc)
• Fpga
• Asic
• Electronics
• Static Timing Analysis
• C