Deepak Chamalla
SoC Functional Validation Engineer | DDR5/LPDDR5 | Post-Silicon Debug | Embedded Systems | Semiconductor Validation |
- Role
- Sr Post Silicon Validation Engineer at Tessolve
- Location
- Srikakulam, AP, IN
- LinkedIn followers
- 500 followers
About Deepak Chamalla
Experienced SoC Functional Validation Engineer with 6+ years of expertise in post-silicon validation, DDR5/LPDDR5 memory subsystem bring-up, and high-speed interface testing. Specialized in debugging complex SoC and memory IP issues across silicon, FPGA, and emulation environments.Proven track record in validating memory performance, timing, and power across CPU uncore domains and embedded subsystems. Hands-on experience with silicon-level analysis using Trace32, JTAG, oscilloscopes, and firmware tools. Strong background in Python/C-based test automation and validation coverage closure.Skilled at cross-functional collaboration with design, firmware, and analog teams to ensure first-pass silicon success and reliable product performance. Experienced in handling customer-specific validation (Alibaba, Jio, AWS) and managing debug requests for large-scale SoC programs.Passionate about building robust silicon validation strategies, optimizing post-silicon workflows, and contributing to next-generation semiconductor platforms.
Experience
Sr Post Silicon Validation Engineer
Feb 2022 — Present · Bengaluru, IN
Memory(DDR) IP Validation
Education
Sagi rama krishnam raju college of engineering
Bachelor of Engineering - BE, Electrical, Electronics and Communications Engineering
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