Deepak Agarwal
Senior Design Engineer | Ex-Analog Devices| Ex-Intel
- Role
- Senior Lead Engineer at Qualcomm
- Location
- Jaipur, RJ, IN
- LinkedIn followers
- 500 followers
About Deepak Agarwal
Design Engineer with skillset as follows:• Hands on experience in RTL logic for blocks like SRAM controller, UFS controller, power gating controller, memory integration, etc.• Proficient in defining Low Power(UPF) at block.• Experienced in performing fast & efficient ECO implementations at different technology nodes.• Debugging skillset for post Si issues through scan dump, AFD (array freeze dump) and helped defining FIB (Focussed ion Beam).• Hands on experience in static EDA tools like Spyglass CDC-RDC, Lint, SpyglassLP, VCLP.• Experience in doing Synthesis & LEC.• Identifying the Violations and Timing related Issues in synthesis.• Proficient in Synopsys and Cadence tool suits
Experience
Senior Lead Engineer
Apr 2023 — Present · IN
Education
Cambridge court high school
High School, Physics, Chemistry and Maths
2008 — 2009
VIT University
Master’s Degree, VLSI Design
2015 — 2017
Kautilya Institute of Technology and Engineering
Bachelor’s Degree, Electronics and Communications Engineering
2009 — 2013
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