Deekshith Krishnegowda
RTL Design @ Marvell Technology
- Role
- Rtl Design Engineer 4 at Marvell Technology
- Location
- Santa Clara, CA, US
- LinkedIn followers
- 500 followers
About Deekshith Krishnegowda
Experienced with RTL/SoC design, IP integration, LEC, CDC, ECO, pre & post silicon power analysis & GLS. Basic knowledge of scan simulations. Interested in working on Low Power Design.
Experience
Rtl Design Engineer 4
Apr 2023 — Present · Santa Clara, CA, US
DataCenter Engineering Group. Working on Marvell\'s high-speed Ethernet PHY/retimer chips for line card/AEC. Successful taped out multiple 400G, 800G & 1.6T chips with complete ownership of subsystems such as MCU and ANLT.
Education
Dayananda Sagar Institutions
Bachelor's degree, Electrical, Electronics and Communications Engineering
2012 — 2016
San José State University
Master's degree, Electrical and Electronics Engineering
2017 — 2019
Skills
- Perl Scripting
- Static Timing Analysis
- Digital Electronics
- Microsoft Office
- Rtl Coding
- Universal Verification Methodology (Uvm)
- Application-Specific Integrated Circuits (Asic)
- Leadership
- Verilog
- Assertion Based Verification
- System Verilog
- Very-Large-Scale Integration (Vlsi)
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