Deekshitha G
FPGA Design Verification Engineer @Capgemini | RTL Design | Verilog, SystemVerilog, UVM | Xilinx, Synopsys, Cadence Virtuoso
- Role
- Design Verification Engineer at Capgemini Engineering
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Deekshitha G
I am a Design Verification Engineer with a deep interest in digital systems, hardware…
Experience
Design Verification Engineer
Sep 2025 — Present · Bengaluru, IN
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