Deekshitha Domakonda

About Deekshitha Domakonda

Detail-oriented and results-driven VLSI Engineer with 6+ years of experience in RTL design, functionalverification, synthesis, timing analysis, and FPGA prototyping. Skilled in SystemVerilog, Verilog, UVM, SVA, andindustry-standard Synopsys/Cadence toolchains. Known for building scalable verification environments anddelivering optimized, high-quality digital designs for complex SoC and IP-level architectures.6+ years of hands-on experience in RTL development, functional verification, and building verificationstrategies for advanced semiconductor designs.Strong command of SystemVerilog, UVM, and SVA with a focus on creating reusable, scalable, andcoverage-driven verification environments.Deep experience in SoC/IP-level verification, including testbench architecture, stimulus generation, andend-to-end verification planning.Proficient with Synopsys VCS, Design Compiler, PrimeTime and Cadence Xcelium, JasperGold, and Genusfor simulation, synthesis, and formal analysis.Skilled in writing clean, synthesizable RTL that adheres to design rules, coding guidelines, and timingconstraints.Experienced in synthesis and timing closure, including constraint development, static timing analysis, andpower/performance optimization.Hands-on expertise in FPGA prototyping—from RTL-to-bitstream generation to board bring-up anddebugging using ILAs and logic analyzers.

Experience

1. Senior Vlsi Verification Engineer

   Maverick Innogarage

   Dec 2023 — Present

   Coordinated end-to-end UVM-based IP verification for high-performance AXI interconnect IPs, buildingscalable testbench architecture with reusable agents, drivers, monitors, scoreboards, and virtualsequencers.Designed custom layered UVM sequences supporting constrained-random, directed-random, and stresstests to efficiently target corner-case AXI protocol scenarios.Developed extensive SystemVerilog Assertions (SVA) for protocol compliance, timing checks, handshakevalidation, and deadlock detection, strengthening the ABV methodology.Built comprehensive functional coverage models (covergroups, cross-coverage, bins) to track protocolbehaviour, data patterns, burst types, and traffic conditions for coverage closure.Automated large regression suites using Synopsys VCS with compile-time optimizations, multi-threadedexecution, and Jenkins/Git/Gerrit CI for continuous regression, lint, and coverage tracking.Implemented Python-based log parsers and result analysers for automated pass/fail detection, waveformextraction, coverage reporting, and debug data summarization.Created reusable AXI protocol checkers and enhanced scoreboard logic to validate read/write ordering,burst rules, QoS, arbitration fairness, and protocol rule compliance.Improved verification efficiency with UVM factory overrides, configurable components, and optimized UVMphase execution to reduce duplicative code and improve simulation runtime.Added error injection mechanisms to validate robustness under timeout conditions, invalid burst types,protocol violations, and other stress scenarios; built TLM utilities and configurable high-bandwidth AXItraffic generators.Collaborated closely with RTL teams to debug issues using DVE/Verdi waveform analysis, SVA failure traces,and signal-level comparisons; documented detailed verification test plans, sequence flow diagrams, SVAspecs, and coverage closure reports.

Education

• Jawaharlal Nehru Technological University

  Bachelor of Engineering - BE

  2016 — 2020

• Arizona State University

  Master of Science - MSE

  2022 — 2024