Deeksha y

About Deeksha y

SoC Design Verification Engineer with ~6 years of hands-on pre-silicon validation experience at both cluster and SoC levels, primarily in the RAS (Reliability, Availability, and Serviceability) domain for Intel server-class processors.My expertise spans developing SystemVerilog/UVM-based testbenches, verifying PCIe and IO subsystems, and driving RAS feature validation for platforms like Intel Xeon processor. I’ve contributed to robust error-handling architectures, performed regression triage, and collaborated with cross-functional teams to accelerate bug resolution and ensure coverage closure.I’ve also worked on GPU emulation bring-up, leading live-mode debug of PCIe controllers using platforms like Palladium SpeedBridge, and built custom glue logic to overcome critical issues like link-up and enumeration failures.Passionate about solving complex design problems and delivering high-quality silicon, I thrive in technically challenging environments where collaboration, precision, and continuous learning are key.I am currently seeking new job opportunties and can be reached at my email id : d••••••••@gmail.com

Experience

1. System-on-chip Design Verification Engineer

   Intel

   Sep 2020 — Present · IN

   Led RAS verification for Intel Xeon processors, ensuring robust error resilience across IO and PCIedomains. Developed UVM-based tests and collaborated cross-functionally to achieve high coverageand accelerated issue resolution.

Education

• National Institute of Technology Warangal

  Master of Technology - MTech

  2017 — 2019