Debasis Sahu

About Debasis Sahu

Memory and IO IP are core to modern technology, powering faster computing, seamless connectivity, and widespread innovation. With over 99% of global internet traffic running on Broadcom chips, I am proud to be part of this growth story.# I am responsible for driving and delivering Analog(Memory, Mixed Signal, Power Management & IO and RF) Layout across organization I had the privilege to work.# Clear understanding of Memory Compiler Architecture, Various IO and mixed signal IP building blocks.# Silicon Debug and Reliability Study.# I have worked in different technology nodes ranging from 700nm to 20nm CMOS and BiCMOS, BCD process, and 16/10/7/5/3nm FinFet and 2nm GAA, A14 process and delivered analog/IO and memory compilers which are silicon-proven for multiple foundries.#I Worked on System-Level Design for few months which involves Hardware Modeling, Architecture definition, Product Development# Training and Mentoring graduates/postgraduates.# Hiring and retaining high performing team.# Vendor Management, Negotiations for staff augmentation. Differentiation:# Intuitive approach to see the design and layout and asking the right questions, following processes, incorporating the innovative methodology, smart debugging and novel automation are key to quality and on-time deliverable.# Novel methodology and systematic approach for flawless quality and on-time deliverable.# Building a team from scratch. Ramping up and making the team productive within a short span of time.# As a leader, I set priorities for the team, get results across boundaries, ensure an inclusive work environment, develop a team, and manage performance. Planning, providing resources for and directs activities in engineering function to meet schedules, standards, and cost. Cultivates and reinforces appropriate group values. Provided guidance on team development, performance, and productivity issues. Plan and schedule daily tasks.Specialties:## Analog and Mixed-Signal and RF Layout and Verification.## Memory Compiler layout ( SRAM-SP/DP, RF-SP/DP, ROM, TCAM, Multi Port)## Standard Cell / IO Layout.## Silicon Debug and Reliability Study.Long Term Goal :# Passionate about building and promoting Entrepreneurship and impacting Education and Financial System in India.# Entrepreneurial Spirit: Having the vision to set up a technology startup to address global issues locally# You can have 1:1 call with me : https://topmate.io/debasis007

Experience

1. R & d Engineer

   Broadcom

   Mar 2013 — Present · Bengaluru, IN

   Delivery of SRAM Memory Compilers, IO Library Modules, and Analog & Mixed Signal Layout for different product lines/ business units of Broadcom working in a range of process nodes up to 2nm.Set best EDA practices in team to improve productivity and ensure best quality of layout is delivered.

Education

• B.J.B College, Bhubaneswar

  +2 Science, Physics, Chemistry, Mathematics and Electronics

  2000 — 2002

• National Institute of Science and Technology (Autonomous, NBA and NAAC Accredited)

  B.Tech, Electrical and Electronics Engineering

  2003 — 2007

• KLE Technological University - Hubballi (India)

  M.Tech, VLSI and Embedded System

  2007 — 2010

Skills

• Project Implementation
• Project Planning
• Negotiation
• Mixed Signal
• Analog and Mixed Signal / Rf Layouts
• Physical Design
• Contract Negotiations
• Embedded Systems
• Eda
• Debugging
• Silicon
• Contract Negotiation
• Start-Ups
• Very-Large-Scale Integration (Vlsi)
• Project Delivery
• Semiconductors
• Building Customer Relations
• Startup Consulting
• Silicon Debug and Reliability Study
• Cmos
• Team Building
• Static Timing Analysis
• Drc
• Arm
• Vlsi
• Lvs
• Innovative Thinking
• Asic
• Characterization
• Problem Solving
• Operations Management
• Io Design,Modeling,Characterization and Layout
• Physical Verification
• Soc
• Project Execution
• Customer Negotiations
• Offshore Project Management
• Pcb Design
• New Business Development
• Verilog