Debarshi Dutta
Camera Design Verification Lead Senior Engineer at Qualcomm | Ex - Intel
- Role
- Lead Senior Engineer at Qualcomm
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Debarshi Dutta
4+ Years of Technical Expertise on End2End GLS Verification & Validation.2+ Years Of Technical Expertise on End2End Functional Verification & Validation including New Camera IP & Features bringup from scratch, Formal Based Verification, Assertion Based Verification, Functional Coverage, Complex Customer Vector Delivery etc.Hands on Experience of Functional Verification Environment Bring-ups & E2E Testing of New Memory Redundancy, Camera Sensor Controller IP\'s & Fire n Forget Camera Feature, including Formal & Assertion Based Verification of the same & Complete Coverage. Handled Complex Performance & Functional Vector Bringup from scratch & deliver the same to customers as per their requirements in real worldHands on Technical Expertise on various aspects of GLS Verification, Debugs on targeted subsystems like Memory Controllers, CNoC etc. & Full SoC across multiple Tech Nodes.Known for Problem solving & developing solutions for complex / technical issues or limitations, Strive to always develop / optimize on new methodologies. Verification: Functional Design Verification Environment Bringup, BFM integration, New IP & Feature Validation etc, Formal Verification using FPV, Assertion Based Verification, Toggle Coverage etc. contributed towards 3+ SoC / Camera IP Successful E2E Functional Verification for Tapeout featuring some of the most advanced ADAS & Futuristic Camera Features.Design Verification Environment development for Gate Level (GLS) Verification, Timing (SDF) GLS and Power Aware (PAGLS) verification. Contributed towards 9+ SoC Chips successful verification (GLS, Timing GLS & PAGLS) for Tapeout. Automation and Optimization: Multiple Automation & Optimization Bring-ups for Automated GLS Testbench generation, Automation for GLS build + simulation quality checks & reporting, Automated SDF Annotation fix for 1st flop in GLS Partition path, Multiple other Automations done to ensure A0 PRQ quality GLS Delivery every time.Automation to fix auto address offset range updates based on dynamic Register Data size during a Common File Format Vector runs.
Experience
Lead Senior Engineer
Dec 2025 — Present · Bengaluru, IN
Education
Techno India University
BTech - Bachelor of Technology, Electrical, Electronics and Communications Engineering
2015 — 2019
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