Debanjan Kundu

About Debanjan Kundu

Self-motivated and challenge driven individual with 6+ years of experience in Physical…

Experience

1. Senior Design Engineer

   Qualcomm

   Sep 2022 — Present · Bengaluru, IN

   Experienced in design closure for physical aware synthesis in TSMC 4nm, 3nm projects using Fusion Compiler.• Experienced in timing closure for the NSP sub-HM IPs with 5M block size.• Single handedly delivered best in class synthesis netlist with multiple PPA trials and correlation from RTL-A to FC for the very latest architecture for Modem IP.• Developed clear understanding of design, data flow, macro placement, IO locations for floorplan feedback to achieve the frequency push by 35%.• Work in tandem with PD & RTL team for the latest product on 3nm technology and achieved the best QoR numbers.• Understanding the design and analyze the trade-off between power, area and timing along with PD custodians for the best PPA recipe for the block.• Developed good understanding on low power strategies, UPF constructs for multi power domain design.• Experienced in PA-LEC, STA (hierarchical and flat) and CLP for synthesis netlist signoff.• Experienced in constraint management and support for SoC timing signoff.• 7 successful BTO & MTO completed in collaboration with RTL, DFT, Power, PD and SOC team.• Process automation with multiple utilities to reduce manual effort during ECO cycle and last mile of project.

Education

• Netaji Subhash Engineering College

  Bachelor of Technology (B.Tech.)

  2011 — 2015

• Vellore Institute of Technology

  Master of Technology - MTech

  2017 — 2019

Skills

• Core Java
• Public Speaking
• Microsoft Excel
• Powerpoint
• Teamwork
• Cadence Virtuoso
• Matlab
• Verilog Hdl
• Leadership
• Altera Quartus
• Html
• Microsoft Office
• Rtl Design
• Java
• Microsoft Word
• Splunk
• Sql
• Modelsim
• C