Debangshu Das
- Role
- System Validation Engineer at Intel
- Location
- Bengaluru, IN
- LinkedIn followers
- 500 followers
About Debangshu Das
To be a dynamic professional to implement all innovative ideas for the betterment of the…
Experience
System Validation Engineer
Apr 2020 — Present
Post-Silicon Validation on PCIe IP: • Got experience in PCIe functional level validation & compliance validation (PCIeCV4:config space based & Exerciser based: functional level) for Intel’s upcoming graphics platform. • Test development covers features including: LTSSM states validation, Endpoint initiated Speed Change & Width change, PCIe Power management cycles (D0 to D3) & Active State Power management cycles(L1, L1SS), TLP posted & non-posted transactions, Completions with Unsupported Req, Power gating & Clock gating features, validation of upstream & downstream memory/config read/write cycles etc. • Measuring PCIe Bandwidth through tools & Lecroy Analyzer traces. • Got expertise in generating PCIe specific test cases using Lecroy Exerciser & Some Intel internal tools. • Proven knowledge on generating Analyzer traces & debugging the issues.
Skills
- Python
- Microsoft Office
- Powerpoint
- Wlan
- Sql
- Microsoft Excel
- C
- Microsoft Word
- Java
- Engineering
- Programming
- Html
- C++
- Matlab
- Windows
- Perl
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