Debalina P.

About Debalina P.

GPU verification engineer with 9+ years of experience driving IP-level and SoC-level verification for complex, high-performance graphics silicon. I focus on building production-grade UVM/SystemVerilog environments, defining coverage-driven verification strategies, and owning functional closure for highly integrated GPU subsystems.I am currently working as a Lead Verification Engineer on GPU verification at both IP and full-chip SoC levels, validating graphics blocks in isolation as well as in large-scale integration environments. My work involves protocol correctness, corner-case debugging, system-level scenarios, and cross-IP interactions critical to GPU stability, performance, and scalability.Prior I worked for PCIe and CXL.mem, contributing to host-to-device connectivity, coherency, and high-bandwidth data movement that are key enablers for modern discrete and integrated GPU architectures. I collaborate closely with design, architecture, and performance teams, and actively mentor engineers while driving best practices in verification quality and reuse.I bring hands-on experience with functional coverage, SystemVerilog assertions (SVA), and protocol-heavy verification, and have worked on GPU and graphics-centric projects across Intel, Micron, and Ascizen. I’m particularly motivated by debugging hard system-level failures, improving simulation efficiency, and building verification flows that scale with growing GPU complexity.Core strengths:GPU Verification (IP & SoC), UVM/SystemVerilog, Graphics & Integration Verification, PCIe/CXL.mem, Functional Coverage & SVA, System-Level Debug, Technical Leadership & Mentorship

Experience

1. Graphics Hardware Engineer

   Intel

   Jun 2022 — Present

Education

• Utkal University

  Masters of Science, Electronics and Telecommunication

  2009 — 2014

• KENDRIYA VIDYALAYA NO.1, BHUBANESWAR

  10th (AISSE)

  2006 — 2007

• Centurion University of Technology and Management

  M.Tech, VLSI Design

  2014 — 2016

• KENDRIYA VIDYALAYA NO.1, BHUBANESWAR

  +2 Science (AISSCE)

  2008 — 2009