Dhanya Chalissery Jose
- Role
- Cadence
- Location
- Irvine, CA, US
- LinkedIn followers
- 500 followers
About Dhanya Chalissery Jose
Experienced ASIC Physical Design Engineer with a Bachelor’s degree in Electronics and…
Experience
Present
Skills
- Verilog
- Perl
- Physical Design
- Clock Tree Synthesis
- Physical Verification
- Formal Verification
- Cadence Virtuoso
- Drc
- Static Timing Analysis
- Asic
- Cadence
- Primetime
- Soc
- Timing Closure
- Arm
- Eda
- Logic Synthesis
- Floorplanning
- Integrated Circuit Design
- Semiconductors
- Debugging
- Tcl
- Low-Power Design
- Vlsi
- Lvs
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