Shaileshkumar B D

About Shaileshkumar B D

DFX - Comprehensive support from Pad selection for testing to silicon bring-up and customer debug assistance.DFX Design Implementation, Verification, and Silicon Bring-up - encompassing planning, leadership, and delivery.Cross-team interactions: Engaging with RTL Design, PAD Design, Clock Design, Timing, Synthesis, PNR, and PD Synthesis teams. etc.

Experience

1. Sr Dft Engineer

   NVIDIA

   Jan 2011 — Present · Bengaluru, IN

   Design for Testability- DFX- Test planning, implementation, and execution for SOCs & IPs- Setting up verification flow and optimizing processes for Complex SOCs- Development and optimization of flows, targets, and resources- Handling SCAN, MBIST, JTAG, ATPG, and Clocks at both RTL and gate levels with Silicon Bringup- Silicon bring-up planning and debuggin

Education

• Sandeepani School of VLSI Design

  PG Diploma in vlsi, VLSI

• Visvesvaraya Technological University

  BE, Electronics & Communication

  2000 — 2004

• Karnataka Technical Education board

  Diploma in Electronics, Electrical, Electronics and Communications Engineering

  1997 — 2000

Skills

• Asic
• Bist
• Application-Specific Integrated Circuits (Asic)
• Atpg
• Rtl Design
• Scan Insertion
• Automatic Test Pattern Generation (Atpg)
• Soc
• Debugging
• Silicon Debug
• Silicon Bringup
• Processors
• Perl
• Eda
• Project Planning
• Dft
• Test Automation
• System on a Chip (Soc)
• Vhdl
• Simulations
• Very-Large-Scale Integration (Vlsi)
• Verilog
• Testing
• Formal Verification
• Vlsi