Davana N

About Davana N

Functional verification:*Debugs of failing tests.*Developed new test cases as per the new requirement from the customer.*Has done some core-leve debugs.Code Coverage:*Detailed analysis of the coverage report.*Justifying any exclusion.*Identifying any verification gaps and adding new scenarios to tests to improve overall coverage.GLS Verification:*Verifying the GLS flow setup before starting GLS.*Worked on VCD generation.*Debug of failing tests.*Setup, Hold, and Width violation analysis as part of GLS debug.Regression Management:*Running weekly RTL Regression and analyzing the report.*Running weekly GLS and PAGLS regression and analyzing the reports for different corners.Shell Scripting:*Worked on automation script for the project environment to reduce the effort and time as a part of daily process.*Taken measures by writing scripts to manage disk space.*Developed script for violation sorting.Domain Skills:*HDL: Verilog*HVL: System Verilog*Testbench Methodology; Universal Verification Methodology (UVM)*Protocol: Ethernet, ICM, UART, SPI, SRAM, AHB, APB*Debugging Tools: Cadence (Simvision, ICM)*Version Control tool : GIT*Ticketing tool: JIRA*Scripting: Shell

Experience

1. Lead Engineer

   HCLTech

   Aug 2025 — Present

   Client : Renesas

Education

• East West College of Engineering

  B.E, Electronics and Communication Engineering

  2016 — 2020

• Nitte Meenakshi Institute of Technology

  Master of Technology - MTech, VLSI Design and Embedded System