Darshan Dehuniya

About Darshan Dehuniya

Skills-> ASIC frontend verification planning and coverage driven closures-> System verilog based verification using UVM and OVM methodologies-> System Verilog Assertions-> Perl scripting for automation of simulations/regressions/coverageDomain Knowledge-> Good knowledge in DDR3, HBM-> Basic knowledge in DDR4->Wireless Protocol - Bluetooth 4.1 Low Energy-> AMBA APB, AXI and AHB-> Communication Protocol : SPI, UARTProject experience:Feb\'16-Sep\'16(For verification services from ACEIC)-> HBM PHY multichannel IP VerificationAug\'15-Jan\'16(For verification services from ACEIC)-> Multi-modal PHY supporting DDR3/4, fully compliant with DFI 4.1 specificationMay\'2015-July\'15(For verification services from ACEIC)-> Functional Verification of DDR3 test chip using System Verilog and UVM Methodology->Understanding the specification of DDR3, Test Chip, AFI Interface-> Developed Verification Environment in UVM from scratch, Modification of existing DFI components. Integration and bringing up the tests for Testchip from planning to sign off.June\'2014-April\'15 (For ACEIC)-> Development of Verification IP for link layer of Bluetooth LE IP (4.0/4.1)-> Test case Preparation of Register lists, Variable lists and BLE Frame list-> Developed AHB Slave BFM individually which takes information from the HOST and updates the Register Model->Developed INIT, NON_CONN_IND, UPDATE ADV Channel Behavioral Model as part of TB Development->Written LL.T.S compliance Test and verifiedDec\'2013 to May\'\'2014:At Aceic-> Developed in house OVM and UVM testbench environments to verify AMBA AXI,AHB,SPI, UART Cores-> Explored OVM and UVM methodologies.

Experience

1. Sr Design Verification Engineer

   Microsoft

   May 2024 — Present · Bengaluru, IN

Education

• Government Engineering College,Gandhinagar

  Bachelor of Engineering (B.Eng.), Electronics and communication Engineering

  2009 — 2013

Skills

• Perl
• Physical Design
• System Verilog
• Functional Verification
• Verilog
• Uvm
• C
• Microsoft Office
• Vlsi
• Fpga
• Soc
• Asic
• Universal Verification Methodology (Uvm)
• Very-Large-Scale Integration (Vlsi)
• Rtl Design
• Open Verification Methodology
• C++
• Field-Programmable Gate Arrays (Fpga)
• Vhdl
• Application-Specific Integrated Circuits (Asic)
• Linux
• Modelsim
• Xilinx Ise
• Xilinx
• Systemverilog
• Microcontrollers
• Spi