Darshan Eswaraiah Lalithamma
Senior Silicon Engineer
- Role
- Senior Design Verification Engineer at Microsoft
- Location
- San Francisco, CA, US
- LinkedIn followers
- 500 followers
About Darshan Eswaraiah Lalithamma
Senior Silicon Engineer, Azure, Microsoft - 2022 - present Design Verification Enginner - High Speed Ethernet Switches Innovium - 20••••21 ASIC Verification Engineer - 5G Baseband/Radio IPs Ericsson - Apr 2019 to Oct 2019 IP Verification Engineer - Ultra-Path Interconnect, MESH, Cache & Home Agent & Multi Die IPs Intel - Aug 2015 to March 2019 Graduated from Arizona State University with Masters in Electrical Engineering - May 2015 Skills: UVM/OVM,Verilog,System Verilog, VLSI Design, Logic Design, Digital Design, Perl, ASIC Design,Synopsys Verdi/VCS, Cadence SimVision/Indago/VManger, Collage, Nebulon, Formal Verification, ModelSim, Xilinx ISE 14.6
Experience
Senior Design Verification Engineer
Feb 2022 — Present
Education
Arizona State University
Master of Science (M.S.), Electrical and Electronics Engineering, 3.8
2013 — 2015
University of Pennsylvania
Master of Science (M.S.), Electrical Engineering
2012
Siddaganga Institute of Technology, Tumkur
Bachelor of Engineering (BE), Electrical, Electronics and Communications Engineering, 9.52
2007 — 2011
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