Darrell Hubbard

Design Technician @Builders FirstSource

Grand Junction, CO, US
EMAILS
d••••••••@bldr.com
MOBILE NUMBERS
+12•••••••26

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WORK HISTORY

Mar 2025 — Present

Design Technician @Builders FirstSource

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US

EDUCATION

1976 — 1979

Preston Senior High School

Graduate, General

1982 — 1990

Idaho State University

No degree, general

SKILLS

Mixed SignalCircuit DesignLayout ToolsHardware Description LanguageCadence VirtuosoTclAnalogIc LayoutFloorplanningCandence 615Integrated Circuit DesignSemiconductorsLayout Versus Schematic (Lvs)DrcVlsiCmosIntegrated Circuits (Ic)UnixPhysical DesignSolidworksSchematicDesign Rule Checking (Drc)Analog CircuitAsicPllRfApplication-Specific Integrated Circuits (Asic)Physical VerificationEdaVirtuosoPlace & RouteHerculesDebuggingAnalog Circuit DesignLvsCadenceIc

ABOUT DARRELL HUBBARD

As a Sr.Staff IC Layout DesignEngineer at ZEKU Technologies, I lead the IC layout design for an innovative Envelope Tracker device, working with engineers to meet the requirements and specifications for the chip. I have over 40 years of experience in custom layout of analog and mixed signal circuits, including RF analog, memory designs, and full chip place and route.I also designed OP27v-OP8v blocks for a PIMIC chip for the parent company OPPO, a leading smartphone manufacturer. My core competencies include design for manufacturability, physical IC mask design, verification and validation tools, and layout tools. I am proficient in various software and tools, such as Cadence, VXL, Solid Works, Design planer, Cadence APR, Dracula, Hercules, Cadence,Asura, LVS DRC ERC, Unix, Microsoft, Schematic, HDL, and netlist. I am passionate about this industry because I am always learning and want to continue. I am a former J52 jet Mech at USMC, and I have worked at small to large Fortune 100 companies.

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