Darrell Hubbard

About Darrell Hubbard

As a Sr.Staff IC Layout DesignEngineer at ZEKU Technologies, I lead the IC layout design for an innovative Envelope Tracker device, working with engineers to meet the requirements and specifications for the chip. I have over 40 years of experience in custom layout of analog and mixed signal circuits, including RF analog, memory designs, and full chip place and route.I also designed OP27v-OP8v blocks for a PIMIC chip for the parent company OPPO, a leading smartphone manufacturer. My core competencies include design for manufacturability, physical IC mask design, verification and validation tools, and layout tools. I am proficient in various software and tools, such as Cadence, VXL, Solid Works, Design planer, Cadence APR, Dracula, Hercules, Cadence,Asura, LVS DRC ERC, Unix, Microsoft, Schematic, HDL, and netlist. I am passionate about this industry because I am always learning and want to continue. I am a former J52 jet Mech at USMC, and I have worked at small to large Fortune 100 companies.

Experience

1. Design Technician

   Builders FirstSource

   Mar 2025 — Present · US

Education

• Preston Senior High School

  Graduate, General

  1976 — 1979

• Idaho State University

  No degree, general

  1982 — 1990

Skills

• Mixed Signal
• Circuit Design
• Layout Tools
• Hardware Description Language
• Cadence Virtuoso
• Tcl
• Analog
• Ic Layout
• Floorplanning
• Candence 615
• Integrated Circuit Design
• Semiconductors
• Layout Versus Schematic (Lvs)
• Drc
• Vlsi
• Cmos
• Integrated Circuits (Ic)
• Unix
• Physical Design
• Solidworks
• Schematic
• Design Rule Checking (Drc)
• Analog Circuit
• Asic
• Pll
• Rf
• Application-Specific Integrated Circuits (Asic)
• Physical Verification
• Eda
• Virtuoso
• Place & Route
• Hercules
• Debugging
• Analog Circuit Design
• Lvs
• Cadence
• Ic