Daniel Dongwook Kim

About Daniel Dongwook Kim

Experience with rtl to Tapeout GDS Flow for 300+ Tapeouts up to 3nm FinFET TSMC and Samsung up to 5nm. Specialties: • Multi Million Gate & High Frequency & Low Power Physical Design & Timing Closure for top level. • Including Hierachical Floorplan, Place & Route, Clock Tree Synthesis, Crosstalk Analysis(SI), IR Drop Checks, Static Timing Analysis, Signal & Power EM Analysis, Logical Equivalence Checks, Mixed Signal Design and Multi Power Domains- Physical Verification with CalibreDRC, LVS, ANT, DFM and LVL

Experience

1. Asic Engineering Technical Leader

   Cisco

   Jan 2025 — Present · San Francisco, CA, US

Education

• SamSung Institute of Technology (SSIT)

  Semiconductor Engineering

• Gumi National Electronic Technical High School

  Electrical and Electronics Engineering

Skills

• Static Timing Analysis
• Physical Verification
• Physical Design
• Timing Closure
• Mixed Signal
• Clock Tree Synthesis
• Floorplanning
• Primetime
• Soc
• Cadence Virtuoso
• Low-Power Design
• Synopsys Tools
• Calibre
• Tcl-Tk
• Verilog
• Formal Verification
• Place & Route
• Drc
• Lvs
• Asic
• Eda
• Tcl