Dandagala Bharath Kumar

About Dandagala Bharath Kumar

I’m an aspiring VLSI Design and Verification Engineer, currently undergoing advanced training at Maven Silicon, where I\'m gaining hands-on experience in RTL design, functional verification and industry-standard methodologies like SystemVerilog and UVM.With a strong foundation in digital electronics and semiconductor fundamentals, I’ve developed and verified RTL modules as part of real-time projects during my training. I’m passionate about the chip design flow—from specification to simulation—and deeply interested in ASIC SoC verification, testbench development, and debugging complex logic. Skills & Tools:• RTL Design (Verilog/SystemVerilog)• Functional Verification using UVM• Testbench architecture and simulation• Scripting (Perl)• EDA tools (Xilinx ISE, Synopsys VCS, Mentor Graphics (Questasim), Synopsys Design Compiler, VC Spyglass Lint )Now I\'m looking for an opportunity where I can contribute, learn from industry experts, and grow as a VLSI professional. My goal is to be a part of cutting-edge semiconductor innovation that shapes the future of electronics.

Experience

1. Advanced Vlsi Design and Verification Trainee

   Maven Silicon

   Feb 2025 — Present · Bengaluru, IN

Education

• TECH JUNIOR COLLEGE

  Intermediate , MPC

• Chadalawada Ramanamma Engineering College , Tirupati

  Bachelor of Technology - BTech, Electrical, Electronics and Communications Engineering

  2020 — 2024

• MASTHAN VIGNAN ENGLISH MEDIUM HIGH SCHOOL

  SSC