Crystal Tara
Memory Validation Engineer at Intel Corporation
- Role
- System Validation Engineering Manager at Intel
- Location
- Hillsboro, OR, US
- LinkedIn followers
- 500 followers
Experience
System Validation Engineering Manager
Jun 2024 — Present
Led and mentored a team of 7 engineers responsible for post-silicon memory bring-up, characterization, and validation. • Owned execution and delivery of test chip products, driving validation readiness from early silicon through stable enablement. • Prioritized validation throughput across multiple concurrent projects, ensuring schedule alignment with product milestones. • Acted as escalation point for complex silicon and memory issues, enabling rapid root-cause analysis and resolution.
Education
University of Southern California
Master's Degree, Electrical and Electronics Engineering
2012 — 2014
Skills
- Computer Architecture
- Testing
- Real-Time Data Acquisition
- Spice
- Embedded C
- Cadence Virtuoso
- Agile Methodologies
- Synopsys Tools
- Data Acquisition
- Encounter
- Integrated Circuit Design
- Cadence Spectre
- Perl
- Low Power Systems
- Design Compiler
- Assembly Language
- Synopsys Primetime
- C++
- C
- Xilinx Ise
- Python
- Emulation
- Vlsi
- Rtl Design
- Linux
- Quality Center
- Modelsim
- System Testing
- Verilog
- Ni Labview
- Ncsim
- X86 Assembly
- Asic
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