Chirag N. Paunwala
Professor and Head, E&C Dept, SCET, Surat | Chair IEEE Gujarat Section |Director, IEEE SPS Membership Development | Advisor, IEEE SPS Gujarat Section | Project Lead, R10 ACEI, IEEE Gujarat Section
- Role
- Director Mebership Development at Ieee Signal Processing Society
- Location
- Surat, GJ, IN
- LinkedIn followers
- 500 followers
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About Chirag N. Paunwala
Prof Chirag Paunwala obtained his Ph.D. from NIT, Surat. He has completed M.E.(Digital…
Experience
Director Mebership Development
Ieee Signal Processing Society
Jan 2025 — Present
Education
Rajiv Gandhi Prodyogiki Vishwavidyalaya
M.E.
2004 — 2006
Sarvajanik College of Engineering & Technology
B.E.
1995 — 1999
Sardar Vallabhbhai National Institute of Technology, Surat
Doctor of Philosophy (Ph.D.)
2008 — 2012
Skills
- Simulations
- Artificial Intelligence
- Machine Learning
- Algorithms
- Digital Image Processing
- Opencv
- Opengl
- Programming
- Computer Vision
- Signal Processing
- Pattern Recognition
- Image Processing
- Matlab
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