Cory Ellinger

About Cory Ellinger

Static Timing Analysis engineer with experience in processors, SoC, mixed signal designs,…

Experience

1. Senior Principal Engineer

   Marvell Technology

   Apr 2017 — Present

   Static Timing Analysis (STA) engineer for Marvell\'s Octeon 10 family of DPU products. Octeon 10 is the industry\'s first processor family based on 5nm ARM Neoverse N2 platform. Key features of the design family: 8 to 36 64-bit ARM Neoverse N2 cores with speeds up to 2.5 GHz Up to 36 MB L2 and 72 MB L3 cache Up to 12 DDR5 at 5200 MTS Comprehensive hardware accelerators- Hardware ML/AI Acceleration Engine- Hardware based VPP accelerator - Integrated 1Tb switch- True inline crypto- Highly programmable packet processors- Secure Boot - Physically unclonable function (PUF)- PCIe DMA Acceleration • Rich set of I/O - 8-36 PCIe Gen 5 lanes - Up to 16 x50G ethernet lanes- Up to 56G SerDes lanes

Education

• George Mason University - College of Engineering and Computing

  MS, Computer Engineering

  2000 — 2006

Skills

• Microprocessors
• Vhdl
• System on a Chip (Soc)
• Digital Design
• Static Timing Analysis
• Vlsi
• Embedded Systems
• Integrated Circuit Design
• Application-Specific Integrated Circuits (Asic)
• Physical Design
• Cadence Virtuoso
• Lvs
• Linux
• Unix
• Hardware
• Timing
• Tcl
• Semiconductors
• C
• Verilog
• Cmos
• Eda
• Ic
• Processors
• Asic
• Electronics
• Perl
• Electrical Engineering
• Analog
• Wireless
• Dft
• Soc
• Floorplanning
• Mixed Signal
• Timing Closure
• Primetime
• Hardware Design