Colin Wise
Physical Design Technical Lead @Fractile
Windsor, GB
EMAILS
MOBILE NUMBERS
+91 *********19
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WORK HISTORY
Jan 2026 — Present
Physical Design Technical Lead @Fractile
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London, GB
EDUCATION
1990 — 1996
Bethany School
A Level, Maths, Physics and Geology
1996 — 2000
University of Bristol
Masters of Electrical and Electronic Engineering, Electrical and Electronics Engineering
SKILLS
EdaMixed SignalCmosStatic Timing AnalysisVhdlRtl DesignSemiconductorsDebuggingElectronicsSocFpgaAsicVerilogHardware ArchitectureVlsiLogic SynthesisIc
ABOUT COLIN WISE
20+ years of experience in ASIC physical implementation in nodes down to 3nm.Chip and subchip physical design implementation within Synopsys (DC, ICC2, FC, Primetime) and Cadence (Genus, Innovus, Tempus, Voltus) toolsets.Chip level verification including STA, DRC, LVS & LEC.
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