Ciricilla Manasa
SMTS Silicon Design Engineer at AMD
- Role
- Smts Silicon Design Engineer at AMD
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Smts Silicon Design Engineer
Jul 2022 — Present
Education
Jawaharlal Nehru Technological University
M.Tech
2009 — 2011
Jawaharlal Nehru Technological University
B.tech
2005 — 2009
Skills
- Fpga
- Asic
- Scripting
- Tcl
- Systemverilog
- Integrated Circuit Design
- C
- Verilog
- Soc
- Smart Worker
- Physical Design
- Application-Specific Integrated Circuits (Asic)
- System on a Chip (Soc)
- Vlsi
- Logic Design
- Rtl Design
- Perl
- Static Timing Analysis
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