Chris Tippett

About Chris Tippett

Vast experience leading teams for the design of digital mixed-signal systems.• $1.5B+ in net revenue for projects as the Digital Design Lead and/or PL Design Manager• Requested by name by Tier1 customers for project support outside of own Business Unit• Methodology Development Expertise- RTL to GDS Design Flows- Auto-Generated Design Verification Environment- Structured Design Procedures, Coding Guidelines, IP Reuse KitsProduct Spaces • Linear and switched-mode battery charging (mobile, accessories, and wearables)• USB Smart Switching Applications• LED cooling• Audio/Microphone Sensing/Switching Applications• Ultrasonic Flow Metering• Mobile User Interface Applications (touchscreen, remote peripherals, etc.)• Tunable RF Antenna Matching Control• Serial Interfaces (I2C, SPI, HDQ, MIPI RFFE, USB)• Dithering PLLsDevelopment Details • Multi-million gate SOCs (for which I was designing multi-GHz SERDES) to small mixed signal control systems operating at Hz clock frequencies• Silicon process nodes from 350nm to 65nm• Project development cycles as long as 2 years to cycles and as short as 8 weeks• Several custom developments for single customers (Apple, FitBit, Google, nVidia) and several catalog developments for mass market• Roles as design manager, chip owner, design sub-system owner, sub-system DV owner, general digital supportSkillset• RTL design using Verilog and SystemVerilog• Verification using Automatic Checking Testbenches• Transaction Level Modeling in SystemVerilog• Code Coverage Analysis• Synthesis• Scan Insertion• Place and Route• Logical Equivalence Checking• Static Timing Analysis• Interfacing with Cadence Analog tools such as Virtuoso Analog Design Environment

Experience

1. Senior Principal Digital Design Engineer

   Analog Devices

   Nov 2024 — Present · Dallas-Fort Worth, TX, US

Education

• Oklahoma State University

  BSEE, Electrical and Computer Engineering

  1993 — 1998

Skills

• Asic
• Mixed Signal
• Soc
• Verilog
• Integrated Circuit Design
• Ic
• Perl
• Rtl Design
• Tcl
• Dft
• C
• Timing Closure
• Cadence Virtuoso
• Debugging
• Cmos
• Pll
• Signal Integrity
• Electrical Engineering
• Unix
• Static Timing Analysis
• Circuit Design
• Modelsim
• Verilog-a
• Logic Design
• Matlab
• C++
• Linux
• Windows
• Primetime
• Shell Scripting
• Ncsim
• Scripting
• Cvs
• Nc-Verilog
• Digital Design
• Usb
• Vcs
• Simulation
• Serdes
• Logic Analyzer