Chintan Patel
Senior Design Verification Engineer at Google
- Role
- Senior Design Verification Engineer at Google
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Chintan Patel
10+ years of experience in ASIC Verification- Experience on USB 2.0, AMBA AHB, APB, AXI, SMMUv3 protocol- Practical exposure of working in various phases of Verification IP development- Experience in RTL Functional Verification and Functional & Code Coverage- Experience in Constrained Driven Verification (CDV) & regression management- Hands-on expertise of working on Test Plan & Test bench development in UVM environment- Proficient in writing test cases, simulation and debugging- Experience in building verification environment from scratch using Verilog, SystemVerilog and methodologies like UVM- Good Understanding of ASIC Design Flow and Design Verification Techniques.
Experience
Senior Design Verification Engineer
May 2024 — Present
Education
L.D.R.P institute of technology
Bachelor of Engineering (BE), electronics and communication engineering
2008 — 2012
Skills
- Microcontrollers
- Simulations
- Code Coverage
- Digital Designs
- Static Timing Analysis
- Logic Design
- Fsm Based Design
- Verilog
- Functional Verification
- Functional Coverage
- Rtl Coding
- Asic
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