Chinmay Hegde
Mixed Signal Logic Design Engineer | Intel | MIT, Manipal | RVCE
- Role
- Mixed Signal Logic Design Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Chinmay Hegde
I’m an RTL Design Engineer at Intel with hands-on experience on RTL quality checks, including CDC/RDC analysis and assertion-based verification, ensuring design robustness from the ground up. I’ve also worked on ATPG for mixed-signal IPs. Skilled in Verilog, SystemVerilog, and tools like Design compiler, VCS, Tessent & Xcelium, I’m passionate about low-power design and I aspire to contribute to cutting-edge, power-efficient SoC and IP development. I actively seek opportunities that allow me to apply my technical strengths, attention to detail, and continuous learning mindset to create robust, efficient digital hardware solutions.#Microelectronics #Electronics #SemiconductorDevices #VLSIDesign
Experience
Mixed Signal Logic Design Engineer
Jun 2025 — Present · Bengaluru, IN
Education
Manipal Institute of Technology
Master's degree, Microelectronics
RV College Of Engineering
Bachelor's degree, Electrical and Electronics Engineering
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.