Ching-Chang
- Role
- Design Verification Engineer at Intel
- Location
- San Jose, CA, US
- LinkedIn followers
- 500 followers
About Ching-Chang
Strong background in memory interface verification in IO subsystem level - Extensive…
Experience
Design Verification Engineer
Aug 2017 — Present
CTO Office Research Projects - Performed interface verification on EMIB/AIB (Advanced Interface BUS) Subsystems in chiplets/DSP/Silicon Photonic applications with FPGAs • Intel® Agilex™ FPGAs - Designed and built scalable DDR4 test environment for 10+ tile-based design variants, targeting high performance memory interface with very high design flexibility - Defined high-level abstraction of memory interface topology for FPGA use models and design changes - Supported management in project execution monitoring, technical details consultation, resource budgeting, and milestone/delivery alignment - Provided domain knowledge training, mentored and coordinated tasks for junior staff and contractors - Defined test cases/coverage, held test plan review and rolled out implementation details
Skills
- Microsoft Office
- Rtl Design
- Vmm
- Spice
- Unix
- Linux
- Uvm
- Soc
- Tcl
- Perl
- Vcs
- Visual Basic
- Verilog
- Functional Verification
- Systemverilog
- Custom Design
- Rtl Coding
- Python
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