Chhavi Saxena
Senior Staff Cpu Verification Engineer @Qualcomm
San Jose, CA, US
EMAILS
c••••••@qti.qualcomm.com
MOBILE NUMBERS
+15•••••••38
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WORK HISTORY
Jun 2025 — Present
Senior Staff Cpu Verification Engineer @Qualcomm
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Santa Clara, CA, US
EDUCATION
2012 — 2014
University of Southern California
Master of Science (MS), Electrical and Electronics Engineering
2008 — 2012
National Institute of Technology, Tiruchirappalli
Bachelor of Technology (B.Tech.), Electronics and Communication Engineering
SKILLS
Rtl DesignFunctional VerificationDebuggingMatlabXilinx IseVhdlFormal VerificationLinuxModelsimCadence NcverilogCadence DivaCadence VirtuosoDigital Circuit DesignC++CSpiceMicrosoft OfficeVlsiCadence SpectrePerlNcsimSystemverilogFpgaLogic DesignAsicCadence SchematicCadence Ade LSimulinkComputer ArchitectureCadenceUvmAltera QuartusVerilogPythonBash
ABOUT CHHAVI SAXENA
Have an interest in RTL Verification and Computer Architecture DesignSPECIALITIES: Functional Verification using C++ and UVM Methodology
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