Chethan K
Design Verification Engineer at Wipro Technology
- Role
- Design Verification Engineer(Project Engineer Vlsi) at Wipro
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Chethan K
ASIC/SOC Design Verification using HVL ( System Verilog) for IP/SOC-verification.* Skills : System Verilog,SVA,TREK,UVM,Verilog.* Protocol Knowledge :AXI,AHB,APB, I2C,SPI,GPIO.
Experience
Design Verification Engineer(Project Engineer Vlsi)
Nov 2014 — Present · Bangalore, IN
Education
Sir MVIT
Master of Technology (M.Tech.)
2010 — 2013
Skills
- Trek
- Very-Large-Scale Integration (Vlsi)
- Systemverilog
- Universal Verification Methodology (Uvm)
- Uvm
- Functional Verification
- Sva
- Modelsim
- Vhdl
- C
- Perl
- Spi
- Amba Ahb
- Asic
- Service Provider Interface (Spi)
- Verilog
- Tcl
- Application-Specific Integrated Circuits (Asic)
- I2c
- Vlsi
- C++
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