Chethan C
Analog Layout Design Engineer
- Role
- Analog Layout Design Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Chethan C
Good Hands on experience in Analog, IO and Standard Cell layout design in deep sub micron technologies(2nm,3nm,5nm,6nm,7nm,10nm) and also in 16nm,45nm,180nnm.• ProcessTechnologies: TSMC, INTEL,Samsung,UMC• Expertise in Layout Design for various blocks (PLL, LDO, ADCs, LVDS_TX and RX, LEVELSHIFTERS, COMPARATORS, DRIVER, Temperature Sensor.)• Physical Verification: DRC, LVS, Density checks, Antenna DRC, ESD/LUP check,Parasitic Extractions on Calibre, PVS, Assura, CPDS.• Expertise in planning Power/Ground structure, Floor Planning, Block Placement,Area Estimation and Routing of critical signals with all the constraints to be taken care.• Good hands on experience in overcoming challenges like Max and Min. base layer and metal density errors, EM violations, Antenna Violations and ESD.
Experience
Analog Layout Design Engineer
Aug 2022 — Present · Bengaluru, IN
Education
J S S Academy of Technical Education, BANGALORE
Bachelor of Engineering (B.E.), Electronics and Communications Engineering
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