Chetan Shah

About Chetan Shah

Objective: Work as an ASIC Design verification engineer, to achieve optimum result and meet schedules by the virtue of technical know-how & expertise, analytical skills, innovative ideas and to grow with the organization in a challenging work environment. Experience: 12 yearsSkills• Functional Verification (HVL, HDL).• Protocols: OTN over packet Fabric Protocol (OFP)(OIF-SAR), Generic Framing Procedure (GFP)(Recommendation ITU-T G.7041/Y.1303), MIPI DigRF, MIPI UniPro • Reusable Methodologies: UVM, VMM, OVM, SVT, SVA.• ASIC Design Methodology and Verification.• Hardware Verification Language (HVL): SystemVerilog.• Hardware Description Language (HDL): Verilog.• FPGA Synthesis and FPGA Prototyping• Simulators: VCS, Questasim• EDA Tools: VCS, DVE, Verdi, Xilinx ISE, Certify.• Programming languages: C, C++• Scripting and automation: Perl, Tcl/Tk, Shell, C-Shell, Makefile• Revision Management : Perforce, CVS• Highly motivated, self-starter that works well on individual and team assignments.• Thrive on challenges and work well under pressure deadlines, while maintaining a good sense ofhumor.

Experience

1. Principal Engineer

   Broadcom

   Oct 2022 — Present · San Jose, CA, US

Education

• Government Polytechnic, Gandhinagar

  Diploma, Electronics & Communication Engineering

  2002 — 2005

• South Gujarat University

  BE, Electronics & Communication Engineering

  2005 — 2008

Skills

• Vlsi
• Semiconductors
• Hardware Design
• System on a Chip (Soc)
• Circuit Design
• Hardware Verification
• Xilinx
• Systemverilog
• Modelsim
• C++
• Microcontrollers
• Functional Verification
• Fpga
• Asic
• Generic Framing Procedure
• Mipi Unipro
• Universal Verification Methodology (Uvm)
• Tcl
• Debugging
• Vip
• Vhdl
• Simulations
• Mipi Digrf
• Application-Specific Integrated Circuits (Asic)
• Coverage Analysis
• Verilog
• Vmm
• Analysis
• Perl
• Embedded Systems
• Field-Programmable Gate Arrays (Fpga)
• Soc
• Hardware
• G.7041
• Simulation
• Emulation
• Uart
• Uvm