Chetana Lahari Pasam

About Chetana Lahari Pasam

4+ years of experience in Physical Design Engineering with expertise in RTL-to-GDSII implementation across advanced technology nodes (3nm to 12nm). • Hands-on experience with hierarchical SoC-level integration, memory subsystem design (LPDDR5/5x, HBM), and bus protocols (AHB/AXI). • Proven track record in timing closure, power integrity (IR/EM analysis), and physical verification (DRC/LVS) using tools like RedHawk, Voltus, Calibre, and ICV. • Skilled in clock tree synthesis, floorplanning, and low-power techniques including clock gating, multi-Vt cell usage, and power-aware simulations. • Proficient in scripting and design automation using Tcl, Python, Perl, and Shell to improve PD and verification workflows. • Strong collaboration with front-end, verification, and architecture teams; contributed to pre-silicon and GLS validation in UVM-based environments. • Experience working in fast-paced semiconductor environments (Samsung, Foxconn) with exposure to SoC development for consumer and automotive domains. • Adept at mentoring junior engineers and supporting EDA tool validation, ensuring robust and scalable design flows. • Strong problem-solving skills and ability to work on complex, high-performance designs while meeting tight deadlines and quality standards

Experience

1. Application Engineer

   Cadence

   Aug 2025 — Present · Austin, TX, US