Chetan B.
ASIC Physical Design Engineer | PnR | PV | STA | EM IR | Low Power I SignOff
- Role
- Asic Physical Design Engineer (Cwf) at Qualcomm
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Chetan B.
I\'m experienced in Physical Design flow, Including Floorplanning, Placement, Clock Tree Synthesis and Routing, using Cadence and Synopsys tools. I\'ve implemented various Optimization techniques for better quality of results. I possess knowledge in Logic Synthesis, Physical Aware Synthesis, Static Timing Analysis and in writing ECOs.
Experience
Asic Physical Design Engineer (Cwf)
Mar 2023 — Present · Bengaluru, IN
ASIC Physical Design Engineer (CWF)- PnR, PV, EM IR, STA Pre-Audit checks, Floor Planning, Placement Optimization, Timing Optimization, Building Clock-Tree, SMART-Routing, Cross-talk Analysis, Sign-off Timing Analysis, Co-relation understanding between Sign-off RC-extraction to PnR-Extraction, EM IR Analysis and Fixes, DRC and LVS fixes and Calibre signoff.
Education
Sathyabama University
Bachelor of Engineering
2016 — 2020
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