Chet Lad
Sr Director, Digital Asic Design at Marvell Technology @Marvell Technology
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WORK HISTORY
Sr Director, Digital Asic Design at Marvell Technology @Marvell Technology
Ottawa, ON, CA
EDUCATION
University of Waterloo
Bachelor of Applied Science (BASc), Electrical and Electronics Engineering
SKILLS
ABOUT CHET LAD
Strong hands-on ASIC design skills including RTL design, Verification, Synthesis, Equivalence, CDC, DFT, ATPG, STA constraint development, Floor-planning, Synopsys/Cadence design flowsDelivered multiple compliant PAM based 50G/100G/200G DSP re-timer and gearbox ASICs targeted for optical modules for inside and intra datacenter connectivityFamiliar with all aspects of a COT ASIC flow from concept through to production including, architecting, front-end design/verification, physical design, product engineering including test (ATE).Managing both domestic and off-shore teams to deliver complex, successful, mixed signal custom production worthy telecom ASICs.Managed state-of-art ASIC verification teams utilizing constrained random-driven verification and functional coverage using UVM methodologies.Chip design project management, project planning, program management, recruitment, resourcing and scheduling leading to multiple production release ASSP devices.Domain knowledge of protocols such as OTN (G.709), Ethernet(802.3), Sonet/SDH, GFP, MLG, 10GBase-R, 10GBase-W, 10GBase-T, 10GBase-KR, SFP+, XFP, OTL, CAUI, PAM4, MLG, SFI-S, Interlaken, PCIe, AMBA, SPI, MDIO, DDRLanguages: Verilog/System Verilog, Perl, TCL, Python
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