Cheera S Jagadish
Senior Verification engineer for PCIE(Gen3 to Gen5) and CXL1.0
- Role
- Contractor at Marvell Technology
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Cheera S Jagadish
I have a good working experience in SV and UVM based functional verification.Protocols Known- PCIe(Gen1 to Gen 5), AXI and APB. work experience on Pcie projects, SPI interface good working knowledge in Failures Debugging, testplan and test development, functional coverage.
Experience
Contractor
Nov 2024 — Present
Education
University of Madras
B. Sc, Electrical and Electronics Engineering
2016 — 2019
University of Madras
Master's degree, Applied electronics
University of Madras
MSC, Applied electronics
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