Cheena Garg
Rtl Design Engineer @Chipspirit
New Delhi, DL, IN
EMAILS
MOBILE NUMBERS
+91 *********19
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WORK HISTORY
Aug 2023 — Present
Rtl Design Engineer @Chipspirit
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Bengaluru, IN
EDUCATION
N/A
Tagore Public School, Palwal
Senior secondary, PCM
N/A
Deenbandhu Chhotu Ram University of Science and Technology, Murthal
Bachelor of Technology - BTech, Electrical, Electronics and Communications Engineering
ABOUT CHEENA GARG
RTL Design Engineer at Chipspirit Technologies | HDL| VLSI |Verilog | Semiconductor | FPGA| Hardware Testing & Compliance | B.Tech in Electronics and Communication Engineering
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