Cheena Garg
VLSI | RTL Design Engineer
- Role
- Rtl Design Engineer at Chipspirit
- Location
- New Delhi, DL, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Cheena Garg
RTL Design Engineer at Chipspirit Technologies | HDL| VLSI |Verilog | Semiconductor | FPGA| Hardware Testing & Compliance | B.Tech in Electronics and Communication Engineering
Experience
Rtl Design Engineer
Aug 2023 — Present · Bengaluru, IN
Education
Tagore Public School, Palwal
Senior secondary, PCM
Deenbandhu Chhotu Ram University of Science and Technology, Murthal
Bachelor of Technology - BTech, Electrical, Electronics and Communications Engineering
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