Tarun Chawla
Senior Staff Engineer @STMicroelectronics
Grenoble, FR
EMAILS
MOBILE NUMBERS
+91 *********19
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WORK HISTORY
Jan 2025 — Present
Senior Staff Engineer @STMicroelectronics
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Crolles, FR
EDUCATION
2001 — 2005
Dhirubhai Ambani Institute of Information and Communication Technology
Bachelors of Technology, Electronics, Communication and Information Technology
2008 — 2009
Alliance Française de Grenoble
Certificate Level B1, French
2007 — 2010
Télécom Paris
PhD, Microelectronics
2005 — 2007
Isep - École d'ingénieurs du numérique
MSc, System on Chip Design (microelectronics)
SKILLS
EdaEtsSpicePowerpointWordApplication-Specific Integrated Circuits (Asic)TclVlsiSemiconductorsEldoExcelSynopsys PrimetimeStatic Timing AnalysisQuality AssuranceAsicIntegrated Circuit DesignPrimetimeMatlabCadenceSiliconVerilogCmos
ABOUT TARUN CHAWLA
Develop, maintain and support SignOff flow methodology for Static Timing Analysis and ECO - Qualification, feature development and testing for Synopsys PrimeTime and Cadence Tempus - 3D-IC timing analysis methodology - Experience in advanced nodes (12nm FINFET, 18nm FDSOI with PCM, 28nm FDSOI)- Experience in multiple silicon debugs
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