Chaturbhuj Rajendran
- Role
- Soc Design Engineer at Intel
- Location
- Austin, TX, US
- LinkedIn followers
- 500 followers
About Chaturbhuj Rajendran
Intel Corporation leverages my expertise as a Physical Design Engineer in the Xeon and…
Experience
Soc Design Engineer
Apr 2019 — Present
SOC Design Engineer responsible for RTL Synthesis, Physical design, Static Timing Analysis, Power optimization, etc of various blocks on Intel’s 7nm and 10nm process nodes in the Xeon and Networking Engineering Group.
Education
Stony Brook University
Master of Science - MS, Electrical and Computer Engineering
2017 — 2018
PES University
Bachelor of Engineering - BE, Electrical, Electronics and Communications Engineering
2012 — 2016
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